According to a conventionally known technique referred to as “test point insertion (TPI)”, a mechanism to observe and control a value of a signal line is inserted in a semiconductor integrated circuit to improve the fault detection rate during a test of the semiconductor circuit.
For example, when a combinational circuit to detect faults is connected to an external terminal or a scan flip flop (hereinafter, referred to as “SFF”) through another combinational circuit, the fault detection rate of the combinational circuit that detects faults decreases consequent to the influence of the other combinational circuit. Therefore, according to a known technique for the TPI, an observation point such as an SFF or an output terminal is connected to the signal line between the combinational circuit that detects faults and the other combination circuit; whereby, observation of the value of the signal line is enabled and the fault detection rate is improved.
When many observation points are present, the circuit area of the semiconductor integrated circuit and the number of output terminals increases. Therefore, according to a conventionally known technique, an exclusive OR circuit whose input terminals are connected to plural signal lines that are to be observed causes the plural signal lines to share an observation point, whereby increases in the circuit area and the number of output terminals is suppressed (see, e.g., Japanese Laid-Open Patent Publication Nos. 2005-135226, H5-249197, H3-296673, and S63-140969).
However, the exclusive OR circuit has a large area and therefore, when an exclusive OR circuit is used as a shared circuit that causes the plural signal lines to share the observation point, the area necessary for the shared circuit becomes large.